This application claims priority to International Application No. PCT/DE00/02604 which was published in the German language on Feb. 15, 2001.
The invention relates to a cascaded sigma-delta modulator, and in particular, to a cascaded sigma-delta modulator converting time-discrete samples into corresponding analogue signals in digital radio communication receiving devices, an error signal, representing the quantization noise, of a sigma-delta modulator of the cascade respectively being fed to the next sigma-delta modulator of said cascade.
In digital-to-analogue converters, for example, used in digital radio communication receiving devices, a digital input signal with 2xe2x80x3 signal states and a fixed sampling frequency fa is usually converted into an analogue signal which is intended to correspond approximately to the digital signal frequency range xe2x88x92fa/2 to +fa/2.
Particularly in the case of high bit widths n, the number of signal states to be recognized by analogue circuitry constitutes a substantial problem. For this reason, a digital signal is interpolated by digital filters, and use is made of what are known as sigma-delta modulators, which substantially reduce the bit width n of a digital signal in conjunction with increased sampling frequency.
The quantization noise produced in the process is transformed into previously unused frequency bands. Particularly efficient for this purpose are structures which achieve shaping of the noise signal by the use of an IIR filter (Infinite Impulse Response filter) of higher order.
A digital-to-analogue converter which uses an IIR filter as interpolation element and one or more sigma-delta modulators to convert the interpolated signals is described, for example, in U.S. Pat. No. 5,786,779. A cascaded sigma-delta modulator for a digital-to-analogue converter is, moreover, shown in DE 197 22 434 C1. A detailed treatment of the design and mode of operation of sigma-delta modulators is given in S. R. Norswothy, R. Schreier, G. Temes: xe2x80x9cDelta-Sigma Data Converters, Theory, Design and Simulationxe2x80x9d, IEEE Press 1997, ISBN 0-7803-1045-4.
There are two approaches to achieving noise shaping in the case of sigma-delta modulators. In a first approach, use is made of feedback loops of higher order. This permits a reduction up to two signal states (1-bit signaling technology), but starting from noise shaping of order 3, leads to possible instabilities in the case of high input signals. Transgressions of the value range can occur very easily. In order to meet this, an input signal of reduced amplitude is used, as well as state memories with clipping properties, as a result of which it is possible to achieve a circuit stability which can be determined empirically. According to another approach, use is made of cascaded structures of first and/or second order, which are of multistage design and therefore exhibit a stable operational performance.
In one embodiment of the invention, there is a cascaded sigma-delta modulator, for inverting time-discrete samples into corresponding analogue signals in digital radio communication receiving devices. The apparatus including, for example, a first sigma-delta modulator in a cascade having an error signal representing the quantization noise, being fed to another sigma-delta modulator in the cascade; and a decision circuit of the ith sigma-delta modulator of the cascade being fed the output signal yixe2x88x921(k) of the preceding ixe2x88x921 sigma-delta modulators.
In one aspect of the invention, the cascaded sigma-delta modulator, the output signal yi(k) has a low number of signal states.
In another aspect of the invention, the cascaded sigma-delta modulator, the number of the signal states is reduced down to two.
In still another aspect of the invention, the cascaded sigma-delta modulator, cascade stages are provided arbitrarily.
In yet another aspect of the invention, the cascaded sigma-delta modulator, the decision circuit of at least one stage of the cascade is extended by an integrator.
In another aspect of the invention, the cascaded sigma-delta modulator, the decision circuit of at least one stage of the cascade is extended by an integrator, and the output value of the integrator is limited to a minimum or a maximum value.
In yet another aspect of the invention, the cascaded sigma-delta modulator, a dither signal {tilde over (r)}(k) is added to the input signal of the last stage of the cascade.
In another aspect of the invention, the cascaded sigma-delta modulator, the decision circuit of the last stage of the cascade is influenced by a dither signal {tilde over (r)}(k)
In still another aspect of the invention, the cascaded sigma-delta modulator, the output signal {tilde over (y)}ixe2x88x921(k) of all preceding cascade stages is fed, in addition to or instead of the summed output signal yixe2x88x921(k) of all preceding ixe2x88x921 sigma-delta modulators, to the decision circuit of the ith sigma-delta modulator of the cascade.